FLIP FLOPS

flip-flops versus latches

Unlike the D latch, the flip-flop output changes only in response to a clock
signal. More specifically, "in a clocked latch, the state is changed whenever the appropriate inputs change and the clock is asserted, whereas in a flip-flop, the state is changed only on a clock edge." So, the latches change whenever the clock is asserted not on its active edge.

Computer science digital architecture books use flip-flops because they are used to write registers on the active edge.

definitions

present-state: the state of Q output of the latch or flip-flop at the time the
input signals are applied or changed

next state: the state of Q output after the latch or flip-flop has reacted to
these input signals

remember that a period on the clock input signifies a falling-edge flip-flop

(edge-triggered) d flip_floP

a d flip-flop has 2 inputs, D (data) and Clk (clock). So, the truth table is
very, very simple. The left side has only 2 columns and the right side only
Q+ column!!

Q+ = D (D is the data input)

The d flip-flop can be drawn using two D-latches and an inverter. The two latches
are connected in a sequence. The inverter is used to inver the clock signal to the
second D-latch. We then have a diagram where the output of the first latch
is called p and the next one is called q (provided that the clock is
inverted on input into the first one -- I have seen it both ways). There is no wraparound of any
of them, unlike with the s-r latch.

In order to figure out the values of the d flip_flop you need to understand
that it is made of the two d latches, and that you figure that the CLK is G
and that the Data is D. (Remember, it is the G input which is not inverted at
any point in the figuring of the D latch).

The data input then to the first gated D-latch is called D. The clock is inverted when
it goes into the first d-latch but not when it goes into the second d-latch.
It provides the G input to the D latch.

Work through the the diagram piece at a time.

s-r flip flop

see http://www.play-hookey.com/digital/rs_nand_flip-flop.html

r sets q to 1, s sets q to 0
this is the same as the s-r latch. Only here, the output Q can only change
in response to a change in the clock.

Unlike the edge triggered d flip-flop where the clock becomes the g signal,
in the s-r flip-flop there are two inputs (s,r) still and an ADDITIONAL input
for the clock input.

There is a difference in interpretation in the output from the clock. For
example, in the latch, Q+ represents the value after a change in the input.
For a flip-flop, it indicates a change after an activating edge.

this one is very subtle. The output of Q (the second latch which is not
inverted) is allowed to change on the up-active edge; however, the output from
the s-r latch with the inverted clock can only change when the clock is
negative (going down). That is because it is inverted. These are indeed
complicated diagrams.

watch that on the exam

j-k flip-flop

the book says "the J-K flip-flop is an extended version of the S-R flip-flop.
The J-K flip-flop has three inputs -- J,K,clk. The J corresponds to S and the
K corresponds to R.

unlike the s-r flip-flop the j,k inputs can both be one at the same time, at
which point the Q changes state from whatever it was to its opposite.

q+ = jq' + k'q

the implementation of the gates and latches looks at first glance identically
like the s-r latch. However, on closer inspection, the q and q' outputs tie
back into a 3-input AND gate.

T flip-flop

http://www.cs.utsa.edu/~castaned/comp-org1-cs2513/sec001/slides/viewable/Lec34-v.pdf

this slide says that a j-k flip-flop is the same as a falling edge triggered T flip-flop. is this true?

what is true, is that the truth value is an exclusive-or, i.e. Q+ = t'q + tq'