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latches

latches and flip-flops have the ability to "remember" their past inputs. So,
the present input depends not only on the present inputs but on past inputs as
well. They are then fundamental components of sequential switching circuits.
Basically, latches and flip-flops are "memory devices which can assume one of
two stable outputs states and which have one or more inputs that can cause
the output state to change."

the symbol tables for latches do not have clock inputs. Flip-flops have clock
inputs. see

flip_flops.txt

present-state: the state of Q output of the latch or flip-flop at the time the
input signals are applied or changed

next state: the state of Q output after the latch or flip-flop has reacted to
these input signals

s-r latch

see

http://www.play-hookey.com/digital/rs_nand_latch.html

it should not be that p does not equal q, or that in other words q != q'
this will happen when r=s=. Hence, simultaneous zeros are disallowed input into the s-r latch.. the link says (quoting) "Note that it is forbidden to have both inputs at a logic 0 level at the same time".

s sets Q to 1 and R sets Q to 0

gated-D latch

The D-latch has 2 inputs, a data input (D) and a gate(G) input. They are not called "S" and "R"inputs. Those are for S-R latches. The G input is often denoted C for clock.

The output is very simple: if clock C is asserted, the latch is "active" state and the output Q mirrors D. If C is deasserted, D is deasserted at 0.

A gated D-latch can be constructed from an s-r latch and gates. The "gated"
refers to the AND gates, which combine the S and R inputs. The gate input is split between two AND gates. One of the AND gates is inverted and supplies one of the other inputs to the other AND gate.
AND gate #1: clock AND (NOT D)
AND gate #2: clock AND D

From the above, you should be able to draw the damn gates, derive a truth
table, and from the truth table draw the K-map and from there come up with the
next-state equation: Q+ = g'q + gd